scg102ag synchronous clock generators pll 2111 comprehensive drive aurora, illinois 60505 phone: 630- 851- 4722 fax: 630- 851- 5040 www.conwin.com bulletin sg134 page 1 of 8 revision 00 date 11 apr 07 issued by eng applications ? sonet / sdh / atm dwdm / fdm dsl-pon interconnects fec (forward error correction) features 3.3v high precision pll accepts 1 of 4 selectable, pre-determined input frequencies 77.76 mhz to 170 mhz output frequencies available. jitter generation oc-192 compliant 1.0? x 0.80? x 0.285?, surface mount rohs compliant
data sheet #: sg134 p age 2 of 8 rev: 00 date: 4/11/07 ? copyright 2007 the connor-winfield corp. all rights reserved specifications subject to change without notice the scg102ag provides high precision phase lock loop frequency translation for the telecommunication applications. the scg102ag product generates lvpecl outputs from an intrinsically low jitter, voltage controlled crystal oscillator. scg102ag is well suited for use in line cards, service termination cards and similar functions to provide reliable reference, phase locked, synchronization for tdm, pdh, sonet and sdh network equipment . the scg102ag provides a jitter filtered, wander following output signal sychronized to a superior stratum or peer input reference signal. the scg102ag includes a lock detect alarm output. the pll control voltage is brought out through a 470 k ? restistor and can be used to determine when the pull range limits are reached.the lvpecl outputs may be put into the tri-state high impedance functional block diagram figure 1 frequency divider loop filter pecl vcxo frequency divider out (pin 9) cout (pin 10) clkin (pin 1) select a (pin 12) select b (pin 13) ld (pin 3) enable/disable (pin 8) monitor (pin 4) microprocessor 470 k ? 10 k ? 10 k ? condition for external testing purposes by asserting a high signal to the enable/disable pin. the scg102ag locks to any one of four pred-determined input frequencies selected using the select (a&b) lines (see table 4). the output may be any single frequency from 77.76 mhz to 170 mhz. the scg102ag is a 3.3 volt component that will typically draw 75ma. the scg102ag is designed to be used in applications that require temperature rating of -40c - 85 c. the scg102ag package typical dimensions are 1.0? x 0.80? x 0.285? (see fig. 2 for maximum dimensions). this product is rohs compliant. absolute maximum rating table 1 symbol parameter minimum nominal maximum units notes vcc power supply voltage -0.3 5.5 volts v i input voltage -0.3 vcc volts ts storage temperature -55 125 c general description
data sheet #: sg134 p age 3 of 8 rev: 00 date: 4/11/07 ? copyright 2007 the connor-winfield corp. all rights reserved specifications subject to change without notice specifications table 2 symbol parameter minimum nominal m aximum units notes f in available input frequencies cmos 8 k 100 m hz pecl 1 m 100 m hz f out output frequencies(lvpecl) 77.76 m 170 m hz vcc supply voltage 3.135 3.3 3.465 v olts i cc supply current 75 100 ma clkin input logic a = cmos cmos 1 d = pecl pecl clkout output logic f = comp. pecl pecl v oh 2.275 v v ol 1.68 v t r /t f rise/fall time 0.5 1 ns sym output symmetry 45 55 % bw bandwidth 20 hz j gen jitter generation rms 0.5 1 ps (12 khz - 20 mhz) j tran jitter transfer 0.1 db 2 apr input frequency tracking 50 ppm t op operating temperature f = -40 85 c c =0 70 c notes: 1.0: only hcmos and lvhcmos is supported for input frequencies < 1mhz 2.0: gr-253-core, sec. 5.6.2.1.2 pin description table 3 pin # connection description 1 clkin input frequency - the scg102ag ac couples the input , this means that the unit is capable of handling hcmos, lvcmos, pecl, lvpecl input signals. 2 gnd ground 3 lock detector logic ?1? indicates that the unit is locked to the input reference logic ?0? indicates that the reference is lost or out of lock range 4 vcxo monitor control voltage level for the pecl oscillator (between 0.3v and 3.0v when locked) 5 ---- missing 6 nc no connection 7 gnd ground 8 enable/disable logic ?0? (or no connect) = output enabled logic ?1? = output disabled (tri-stated) 9 out output 10 cout complementary output 11 nc no connection 12 select a input frequency select control pin. see table 4. 13 select b input frequency select control pin. see table 4. 14 nc no connection 15 gnd ground 16 v cc power supply voltage (3.3 vdc 5%)
data sheet #: sg134 p age 4 of 8 rev: 00 date: 4/11/07 ? copyright 2007 the connor-winfield corp. all rights reserved specifications subject to change without notice input frequency selection table 4 output load and power supply filtering recommendations figure 2 50 ? 50 ? v t -2 v dc (f out ) ** * * it is highly recommended that either a linear regulator or bypass capacitors be used. typical values would be 10 uf, 0.1 uf, 100 pf. frequency divider loop filter pecl vcxo frequency divider out (pin 9) cout (pin 10) clkin (pin 1) select a (pin 12) select b (pin 13) ld (pin 3) enable/disable (pin 8) monitor (pin 4) microprocessor 470 k ? 10 k ? 10 k ? input freq sel a sel b f 1 00 f 2 01 f 3 10 f 4 11
data sheet #: sg134 p age 5 of 8 rev: 00 date: 4/11/07 ? copyright 2007 the connor-winfield corp. all rights reserved specifications subject to change without notice ordering information table 5 10 mhz a 10 khz b 8 khz c 16 khz d 64 khz e 1.024 mhz f 1.048 mhz g 1.544 mhz h 2.048 mhz j 4.096 mhz k 8.192 mhz l 13.00 mhz m 16.384 mhz n 19.44 mhz p 20.48 mhz r 26.00 mhz t 27.00 mhz w 38.88 mhz x 44.736 mhz y 53.10468 mhz z 51.84 mhz 0 61.44 mhz 1 77.76 mhz 2 82.944 mhz 3 112.00 mhz 4 139.264 mhz 5 155.52 mhz 6 166.6286 mhz 7 114.0 mhz 8 125.0 mhz 9 scg102ag- d f f - a 1 p 6 suppl y v olta g e d = 3.3 v dc 5% output t ype f = comp. pecl t emperature rang e c = 0 c to 70 c f = -40 c to 85 c output frequenc y (2 to 9) see chart above. if a custom frequency is desired, enter s followed by the frequency. contact a sales representative for the availabilty of custom frequencies. input frequency (a to 3) see chart above. if more than one frequency is desired, enter s and list all desired frequencies. contact a sales representative for the availabilty of custom frequencies. number of input frequencies 1 = 1 input frequency 2 = 2 input frequencies 3 = 3 input frequencies 4 = 4 input frequencies input logic a = cmos d = pecl sample p ar t number examples: scg-102ag- dff-a1c2 scg-102ag- dff-a4s2, s = 8 khz, 16.384 mhz, 19.44 mhz, 38.88 mhz scg-102ag-dff-d1zs, s = custom frequency for any model, the reference inputs and output frequency must have a common frequency of 2.667hz (8khz/3) ex 1: a model with reference inputs of 8khz, 16khz, 32khz and 64khz with a output frequency of 155.52mhz is valid due to the common frequency of 2.667khz. contact cw regarding models that do not have a input/output common frequency of 2.667khz.
data sheet #: sg134 p age 6 of 8 rev: 00 date: 4/11/07 ? copyright 2007 the connor-winfield corp. all rights reserved specifications subject to change without notice package dimensions figure 3 .800 [ 20.32mm ] 1.000 [25.40mm] .740 [18.80mm] .100 [2.54mm] pin 1 .285 [7.24mm] max. recommended footprint dimensions figure 4 solder profile figure 5 0 50 100 150 200 250 300 0 50 100 150 200 250 300 350 time (sec) temp (c) 221c reflow zone 30/90 sec (min/max) peak temp. 245-255c for 15 sec typ. soaking zone 60-90 sec typ. (2 min max) ramp slope not to exceed 3c/sec
data sheet #: sg134 p age 7 of 8 rev: 00 date: 4/11/07 ? copyright 2007 the connor-winfield corp. all rights reserved specifications subject to change without notice
2111 comprehensive drive aurora, illinois 60505 phone: 630- 851- 4722 fax: 630- 851- 5040 www.conwin.com revision revision date note 00 4/11/07 final release
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